1. Field of the Invention
The present invention relates generally to semiconductor devices, and more specifically to an optimized method for manufacturing gate oxide capacitors including addition of a wafer backside dielectric along with optimized electron implantation flood gun current control.
2. Related Art
In general, gate oxide capacitors are well known. Typical manufacturing yields of gate oxide capacitors, as determined by leakage tests and/or J-Ramp testing, can be less than 30%, and are often as low as 4% depending on processing, capacitor size, and gate oxide thickness.
It is believed that the low yield is, at least in part, attributable to electro-static discharge ("ESD") damage occurring during normal manufacturing processes. In particular, ESD damage is believed to occur during an ion implantation step, where wafer charging leads to the formation of destructive dielectric breakdown voltages (and resultant gate oxide damage).
Therefore, what is needed is a method for making gate oxide capacitors that overcomes manufacturing-related ESD damage. Such a method must not, however, introduce any undesired side effects such as decreased gate oxide capacitor performance or excessively high manufacturing costs.